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NANA SUTISNA

Institut Teknologi Bandung S1 - Teknik Informatika SINTA ID : 6755701
1.517
SINTA Score Overall
594
SINTA Score 3Yr
1.517
Affil Score
594
Affil Score 3Yr
Latest number of Publication and Citations
A Scalable Design of A Full-Stack Real-Time OFDM Baseband Processor for Network-Enabled VLC Systems
Authors : T Adiono, E Setiawan, M Jonathan, R Mulyawan, N Sutisna, I Syafalni, ... IEEE Access, 2024
2024 2 cited
3.5 GHz reflective electromagnetic surfaces for linear-to-circular polarizer
Authors : DA Nurmantris, U Khayam, N Sutisna, A Munir 2024 IEEE Region 10 Symposium (TENSYMP), 1-5, 2024
2024 1 cited
Accelerated Real-Time Local Maxima Detection in Video Streams Using FPGA Technology
Authors : AN Sukarno, Y Salomo, T Adiono, I Syafalni, N Sutisna, R Mulyawan 2024 Asia Pacific Signal and Information Processing Association Annual …, 2024
2024 0 cited
Efficient Real-Time Smart Keyword Spotting Using Spectrogram-Based Hybrid CNN-LSTM for Edge System
Authors : I Syafalni, C Amadeus, N Sutisna, T Adiono IEEE Access 12, 43109-43125, 2024
2024 1 cited
2-bit Reflective Electromagnetic Surface for X-band Beam Control Function
Authors : DA Nurmantris, MN Arira, N Sutisna, A Munir 2024 International Conference on Electromagnetics in Advanced Applications …, 2024
2024 0 cited
Physical Design of RISC-V based System-on-Chip using OpenLane
Authors : M Fauzan, RF Yanuarsyah, MH Hibatullah, R Arisaputra, I Syafalni, ... 2024 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 529-533, 2024
2024 0 cited
Low-Complexity and High-Throughput Number Theoretic Transform Architecture for Polynomial Multiplication in Homomorphic Encryption
Authors : N Sutisna, EJ Brillianshah, I Syafalni, MO Hasanuddin, T Adiono, ... 2024 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2024
2024 1 cited
Leveraging IoT and Machine Learning for Efficient Rice Stock Monitoring and Prediction
Authors : N Sutisna, AP Nugroho, C Jeffrey, PA Irawan, R Ramadhana, ... 2024 Asia Pacific Signal and Information Processing Association Annual …, 2024
2024 0 cited
DMQ: Dual-Mode Q-Learning Hardware Accelerator for Shortest Path and Coverage Area
Authors : I Syafalni, MI Firdaus, N Sutisna, T Adiono, T Juhana, R Mulyawan 2024 IEEE 37th International System-on-Chip Conference (SOCC), 1-6, 2024
2024 0 cited
Optimizing Deep Q-Network for Shortest Path Computation of Mobile Robot Agents
Authors : A Sumarudin, N Sutisna, I Syafalni, BR Trilaksono, T Adiono 2024 Asia Pacific Signal and Information Processing Association Annual …, 2024
2024 0 cited
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Summary

Article Quartile
Research Output
  Scopus GScholar WOS
Article 0 97 22
Citation 0 266 43
Cited Document 0 52 10
H-Index 5 8 3
i10-Index 4 6 2
G-Index 2 2 1
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